View FAN3100_4106738.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FAN3100 -- Single 2A High-Speed, Low-Side Gate Driver
October 2007
FAN3100 Single 2A High-Speed, Low-Side Gate Driver
Features
3A Peak Sink/Source at VDD = 12V 4.5 to 18V Operating Range Dual-Logic Inputs Allow Configuration as Non-Inverting or Inverting with Enable Function Internal Resistors Turn Driver Off If No Inputs 13ns Typical Rise Time and 9ns Typical Fall-Time with 1nF Load Choice of TTL or CMOS Input Thresholds MillerDriveTM Technology Typical Propagation Delay Time Under 20ns with Input Falling or Rising 6-Lead 2x2mm MLP or 5-Pin SOT23 Packages Rated from -40C to 125C Ambient
Description
The FAN3100 2A gate driver is designed to drive an Nchannel enhancement-mode MOSFET in low-side switching applications by providing high peak current pulses during the short switching intervals. The driver is available with either TTL (FAN3100T) or CMOS (FAN3100C) input thresholds. Internal circuitry provides an under-voltage lockout function by holding the output low until the supply voltage is within the operating range. The FAN3100 delivers fast MOSFET switching performance, which helps maximize efficiency in highfrequency power converter designs. FAN3100 drivers incorporate MillerDriveTM architecture for the final output stage. This bipolar-MOSFET combination provides high peak current during the Miller plateau stage of the MOSFET turn-on / turn-off process to minimize switching loss, while providing railto-rail voltage swing and reverse current capability. The FAN3100 also offers dual inputs that can be configured to operate in non-inverting or inverting mode and allow implementation of an enable function. If one or both inputs are left unconnected, internal resistors bias the inputs such that the output is pulled low to hold the power MOSFET off. The FAN3100 is available in a lead-free finish 2x2mm 6-lead Molded Leadless Package (MLP), for smallest size with excellent thermal performance, or industrystandard 5-pin SOT23.
Applications
Switch-Mode Power Supplies High-Efficiency MOSFET Switching Synchronous Rectifier Circuits DC-to-DC Converters Motor Control
Functional Pin Configurations
Figure 1. 2x2mm 6-Lead MLP (Top View)
Figure 2. SOT23-5 (Top View)
(c) 2007 Fairchild Semiconductor Corporation FAN3100 * Rev. 1.0.0
www.fairchildsemi.com
FAN3100 -- Single 2A High-Speed, Low-Side Gate Driver
Ordering Information
Part Number
FAN3100CMPX FAN3100CSX FAN3100TMPX FAN3100TSX
Input Threshold
CMOS CMOS TTL TTL
Thermal Resistance
(1) JL (2) JA
(3) (3)
Package
6-Lead 2x2mm MLP 5-Pin SOT23 6-Lead 2x2mm MLP 5-Pin SOT23
Packing Method
Tape & Reel Tape & Reel Tape & Reel Tape & Reel
4.5C/W 95C/W 4.5C/W 95C/W
58 - 120C/W
150 - 248C/W 58 - 120C/W
(3) (3)
150 - 248C/W
Notes: 1. Typical JL is specified from semiconductor junction to pin 5 lead. 2. Typical JA is dependent on the PCB design and operating conditions, such as air flow. The range of values covers a variety of operating conditions utilizing natural convection with no heatsink on the package. 3. This typical range is an estimate; actual values depend on the application. All packages are lead free per JEDEC: J-STD-020B standard.
Pin Definitions
SOT23 MLP Pin # Pin #
1 3 2 2 3 4 5 1 6 4 Pad 5
Name
VDD AGND GND IN+ INOUT P1 PGND
Pin Description
Supply Voltage. Provides power to the IC. Analog ground for input signals (MLP only). Connect to PGND underneath the IC. Ground (SOT-23 only). Common ground reference for input and output circuits. Non-Inverting Input. Connect to VDD to enable output. Inverting Input. Connect to AGND or PGND to enable output. Gate Drive Output: Held low unless required inputs are present and VDD is above UVLO threshold. Thermal Pad (MLP only). Exposed metal on the bottom of the package; may be left floating or connected to PGND, but NOT suitable for carrying current. Power Ground (MLP only). For output drive circuit; separates switching noise from inputs.
Output Logic with Dual-Input Configuration
IN+
0 0
(4) (4)
IN-
0 1
(4)
OUT
0 0 1 0
1 1
0 1
(4)
Note: 4. Default input signal if no external connection is made.
(c) 2007 Fairchild Semiconductor Corporation FAN3100 * Rev. 1.0.0
www.fairchildsemi.com 2
FAN3100 -- Single 2A High-Speed, Low-Side Gate Driver
Block Diagrams
Figure 3. Simplified Block Diagram (SOT23 Pin-out)
Figure 4. Simplified Block Diagram (MLP Pin-out)
(c) 2007 Fairchild Semiconductor Corporation FAN3100 * Rev. 1.0.0
www.fairchildsemi.com 3
FAN3100 -- Single 2A High-Speed, Low-Side Gate Driver
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
VDD to PGND VDD
Parameter
Min.
-0.3 PGND 0.3 PGND 0.3
Max.
20.0 VDD + 0.3 VDD + 0.3 +260 +150
Unit
V V V C C C kV V
Voltage on IN+ and IN- to PGND Voltage on OUT to PGND
TL TJ TSTG ESD
Lead Soldering Temperature (10 seconds) Junction Temperature Storage Temperature Electrostatic Discharge Protection Level Human Body Model, JEDEC JESD22-A114 Charged Device Model, JEDEC JESD22-C101 -65 4 750
+150
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VDD VIN TA Supply Voltage Range Input Voltage IN+, IN-
Parameter
Min.
4.5 0 -40
Max.
18.0 VDD +125
Unit
V V C
Operating Ambient Temperature
Pin Configurations
IN+ 1 AGND 2 VDD 3
6 IN 5 PGND 4 OUT
Figure 5. 2x2mm 6-Lead MLP (Top View)
Figure 6. SOT23-5 (Top View)
(c) 2007 Fairchild Semiconductor Corporation FAN3100 * Rev. 1.0.0
www.fairchildsemi.com 4
FAN3100 -- Single 2A High-Speed, Low-Side Gate Driver
Electrical Characteristics
Unless otherwise noted, VDD = 12V, TJ = -40C to +125C. Currents are defined as positive into the device and negative out of the device.
Symbol
Supply VDD IDD VON VOFF
Parameter
Operating Range Supply Current Inputs/EN Not Connected Turn-On Voltage Turn-Off Voltage
Conditions
Min.
4.5
Typ.
Max.
18.0
Unit
V mA mA V V
FAN3100C FAN3100T 3.5 3.3
0.20 0.5 3.9 3.7
0.35 0.8 4.3 4.1
Inputs (FAN3100T) VINL_T VINH_T IIN+ IINVHYS IN+, IN- Logic Low Voltage, Maximum IN+, IN- Logic High Voltage, Minimum Non-inverting Input Inverting Input IN+, IN- Logic Hysteresis Voltage IN from 0 to VDD IN from 0 to VDD -1 -175 0.2 0.4 0.8 2.0 175 1 0.8 V V A A V
Inputs (FAN3100C) VINL_C VINH_C IINL IINH VHYS_C Output ISINK ISOURCE IPK_SINK IPK_SOURCE tRISE tFALL tD1, tD2 tD1, tD2 IRVS OUT Current, Mid-Voltage, Sinking
(5)
IN+, IN- Logic Low Voltage IN+, IN- Logic High Voltage IN Current, Low IN Current, High IN+, IN- Logic Hysteresis Voltage IN from 0 to VDD IN from 0 to VDD
30 70 -1 -175 17 175 1
%VDD %VDD A A %VDD
OUT at VDD/2, CLOAD = 0.1F, f = 1kHz OUT at VDD/2, CLOAD = 0.1F, f = 1kHz CLOAD = 0.1F, f = 1kHz CLOAD = 0.1F, f = 1kHz CLOAD = 1000pF CLOAD = 1000pF
2.5 -1.8 3 -3 13 9 7 9 15 16 500 20 14 28 30
A A A A ns ns ns ns mA
OUT Current, Mid-Voltage, Sourcing OUT Current, Peak, Sinking
(6) (5) (5)
(5)
OUT Current, Peak, Sourcing Output Rise Time Output Fall Time
(6)
Output Prop. Delay, CMOS Inputs Output Prop. Delay, TTL Inputs
(6)
(6)
0 - 12VIN; 1V/ns Slew Rate 0 - 5VIN; 1V/ns Slew Rate
Output Reverse Current Withstand
(5)
Note: 5. Not tested in production. 6. See Timing Diagrams of Figure 7 and Figure 8.
(c) 2007 Fairchild Semiconductor Corporation FAN3100 * Rev. 1.0.0
www.fairchildsemi.com 5
FAN3100 -- Single 2A High-Speed, Low-Side Gate Driver
Timing Diagrams
90% Output 10% VINH VINL tD1 tRISE
Figure 7. Non-Inverting
90% Output 10% VINH VINL tD1
tFALL
Input
Input
tD2
tD2 tFALL tRISE
Figure 8. Inverting
(c) 2007 Fairchild Semiconductor Corporation FAN3100 * Rev. 1.0.0
www.fairchildsemi.com 6
FAN3100 -- Single 2A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
Typical characteristics are provided at 25C and VDD=12V unless otherwise noted.
Figure 9. IDD (Static) vs. Supply Voltage
Figure 10. IDD (Static) vs. Supply Voltage
Figure 11. IDD (No-Load) vs. Frequency
Figure 12. IDD (No-Load) vs. Frequency
Figure 13. IDD (1nF Load) vs. Frequency
(c) 2007 Fairchild Semiconductor Corporation FAN3100 * Rev. 1.0.0
Figure 14. IDD (1nF Load) vs. Frequency
www.fairchildsemi.com 7
FAN3100 -- Single 2A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics (Continued)
Typical characteristics are provided at 25C and VDD=12V unless otherwise noted.
Figure 15. IDD (Static) vs. Temperature
Figure 16. IDD (Static) vs. Temperature
Figure 17. Input Thresholds vs. Supply Voltage
Figure 18. Input Thresholds vs. Supply Voltage
Figure 19. Input Threshold % vs. Supply Voltage
(c) 2007 Fairchild Semiconductor Corporation FAN3100 * Rev. 1.0.0 www.fairchildsemi.com 8
FAN3100 -- Single 2A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics (Continued)
Typical characteristics are provided at 25C and VDD=12V unless otherwise noted.
Figure 20. Input Thresholds vs. Temperature
Figure 21. Input Thresholds vs. Temperature
Figure 22. UVLO Thresholds vs. Temperature
Figure 23. UVLO Hysteresis vs. Temperature
Figure 24. Propagation Delay vs. Supply Voltage
(c) 2007 Fairchild Semiconductor Corporation FAN3100 * Rev. 1.0.0 9
Figure 25. Propagation Delay vs. Supply Voltage
www.fairchildsemi.com
FAN3100 -- Single 2A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics (Continued)
Typical characteristics are provided at 25C and VDD=12V unless otherwise noted.
Figure 26. Propagation Delay vs. Temperature
Figure 27. Propagation Delay vs. Temperature
Figure 28. Propagation Delay vs. Temperature
Figure 29. Propagation Delay vs. Temperature
Figure 30. Fall Time vs. Supply Voltage
(c) 2007 Fairchild Semiconductor Corporation FAN3100 * Rev. 1.0.0
Figure 31. Rise Time vs. Supply Voltage
www.fairchildsemi.com 10
FAN3100 -- Single 2A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics (Continued)
Typical characteristics are provided at 25C and VDD=12V unless otherwise noted.
Figure 32. Rise and Fall Time vs. Temperature
Figure 33. Rise/Fall Waveforms with 1nF Load
Figure 34. Rise/Fall Waveforms with 10nF Load
(c) 2007 Fairchild Semiconductor Corporation FAN3100 * Rev. 1.0.0
www.fairchildsemi.com 11
FAN3100 -- Single 2A High-Speed, Low-Side Gate Driver
Applications Information
The FAN3100 offers TTL or CMOS input thresholds. In the FAN3100T, the input thresholds meet industrystandard TTL logic thresholds, independent of the VDD voltage, and there is a hysteresis voltage of approximately 0.4V. These levels permit the inputs to be driven from a range of input logic signal levels for which a voltage over 2V is considered logic high. The driving signal for the TTL inputs should have fast rising and falling edges with a slew rate of 6V/s or faster, so the rise time from 0 to 3.3V should be 550ns or less. With reduced slew rate, circuit noise could cause the driver input voltage to exceed the hysteresis voltage and retrigger the driver input, causing erratic operation. In the FAN3100C, the logic input thresholds are dependent on the VDD level and, with VDD of 12V, the logic rising edge threshold is approximately 55% of VDD and the input falling edge threshold is approximately 38% of VDD. The CMOS input configuration offers a hysteresis voltage of approximately 17% of VDD. The CMOS inputs can be used with relatively slow edges (approaching DC) if good decoupling and bypass techniques are incorporated in the system design to prevent noise from violating the input voltage hysteresis window. This allows setting precise timing intervals by fitting an R-C circuit between the controlling signal and the IN pin of the driver. The slow rising edge at the IN pin of the driver introduces a delay between the controlling signal and the OUT pin of the driver.
Figure 35. MillerDriveTM Output Architecture
Under-Voltage Lockout
The FAN3100 start-up logic is optimized to drive ground referenced N-channel MOSFETs with a under-voltage lockout (UVLO) function to ensure that the IC starts up in an orderly fashion. When VDD is rising, yet below the 3.9V operational level, this circuit holds the output low, regardless of the status of the input pins. After the part is active, the supply voltage must drop 0.2V before the part shuts down. This hysteresis helps prevent chatter when low VDD supply voltages have noise from the power switching. This configuration is not suitable for driving high-side P-channel MOSFETs because the low output voltage of the driver would turn the P-channel MOSFET on with VDD below 3.9V.
MillerDriveTM Gate Drive Technology
FAN3100 drivers incorporate the MillerDriveTM architecture shown in Figure 35 for the output stage, a combination of bipolar and MOS devices capable of providing large currents over a wide range of supply voltage and temperature variations. The bipolar devices carry the bulk of the current as OUT swings between 1/3 to 2/3 VDD and the MOS devices pull the output to the high or low rail. The purpose of the MillerDriveTM architecture is to speed up switching by providing the highest current during the Miller plateau region when the gate-drain capacitance of the MOSFET is being charged or discharged as part of the turn-on / turn-off process. For applications that have zero voltage switching during the MOSFET turn-on or turn-off interval, the driver supplies high peak current for fast switching even though the Miller plateau is not present. This situation often occurs in synchronous rectifier applications because the body diode is generally conducting before the MOSFET is switched on. The output pin slew rate is determined by VDD voltage and the load on the output. It is not user adjustable, but if a slower rise or fall time at the MOSFET gate is needed, a series resistor can be added.
VDD Bypass Capacitor Guidelines
To enable this IC to turn a power device on quickly, a local, high-frequency, bypass capacitor CBYP with low ESR and ESL should be connected between the VDD and GND pins with minimal trace length. This capacitor is in addition to bulk electrolytic capacitance of 10F to 47F often found on driver and controller bias circuits. A typical criterion for choosing the value of CBYP is to keep the ripple voltage on the VDD supply 5%. Often this is achieved with a value 20 times the equivalent load capacitance CEQV, defined here as Qgate/VDD. Ceramic capacitors of 0.1F to 1F or larger are common choices, as are dielectrics, such as X5R and X7R, which have good temperature characteristics and high pulse current capability. If circuit noise affects normal operation, the value of CBYP may be increased to 50-100 times the CEQV, or CBYP may be split into two capacitors. One should be a larger value, based on equivalent load capacitance, and the other a smaller value, such as 1-10nF, mounted closest to the VDD and GND pins to carry the higherfrequency components of the current pulses.
(c) 2007 Fairchild Semiconductor Corporation FAN3100 * Rev. 1.0.0
www.fairchildsemi.com 12
FAN3100 -- Single 2A High-Speed, Low-Side Gate Driver
Layout and Connection Guidelines
The FAN3100 incorporates fast reacting input circuits, short propagation delays, and powerful output stages capable of delivering current peaks over 2A to facilitate voltage transition times from under 10ns to over 100ns. The following layout and connection guidelines are strongly recommended: Keep high-current output and power ground paths separate from logic input signals and signal ground paths. This is especially critical when dealing with TTL-level logic thresholds. Keep the driver as close to the load as possible to minimize the length of high-current traces. This reduces the series inductance to improve highspeed switching, while reducing the loop area that can radiate EMI to the driver inputs and other surrounding circuitry. The FAN3100 is available in two packages with slightly different pinouts, offering similar performance. In the 6-pin MLP package, Pin 2 is internally connected to the input analog ground and should be connected to power ground, Pin 5, through a short direct path underneath the IC. In the 5-pin SOT23, the internal analog and power ground connections are made through separate, individual bond wires to Pin 2, which should be used as the common ground point for power and control signals. Many high-speed power circuits can be susceptible to noise injected from their own output or other external sources, possibly causing output retriggering. These effects can be especially obvious if the circuit is tested in breadboard or non-optimal circuit layouts with long input, enable, or output leads. For best results, make connections to all pins as short and direct as possible. The turn-on and turn-off current paths should be minimized as discussed in the following sections. Figure 36 shows the pulsed gate drive current path when the gate driver is supplying gate charge to turn the MOSFET on. The current is supplied from the local bypass capacitor, CBYP, and flows through the driver to the MOSFET gate and to ground. To reach the high peak currents possible, the resistance and inductance in the path should be minimized. The localized CBYP acts to contain the high peak current pulses within this driver-MOSFET circuit, preventing them from disturbing the sensitive analog circuitry in the PWM controller.
Figure 37 shows the current path when the gate driver turns the MOSFET off. Ideally, the driver shunts the current directly to the source of the MOSFET in a small circuit loop. For fast turn-off times, the resistance and inductance in this path should be minimized.
Figure 37. Current Path for MOSFET Turn-Off
Truth Table of Logic Operation
The FAN3100 truth table indicates the operational states using the dual-input configuration. In a noninverting driver configuration, the IN- pin should be a logic low signal. If the IN- pin is connected to logic high, a disable function is realized, and the driver output remains low regardless of the state of the IN+ pin.
IN+
0 0 1 1
IN0 1 0 1
OUT
0 0 1 0
In the non-inverting driver configuration in Figure 38, the IN- pin is tied to ground and the input signal (PWM) is applied to IN+ pin. The IN- pin can be connected to logic high to disable the driver and the output remains low, regardless of the state of the IN+ pin.
Figure 38. Dual-Input Driver Enabled, Non-Inverting Configuration In the inverting driver application shown in Figure 39, the IN+ pin is tied high. Pulling the IN+ pin to GND forces the output low, regardless of the state of the IN- pin.
Figure 36. Current Path for MOSFET Turn-On
Figure 39. Dual-Input Driver Enabled, Inverting Configuration
www.fairchildsemi.com 13
(c) 2007 Fairchild Semiconductor Corporation FAN3100 * Rev. 1.0.0
FAN3100 -- Single 2A High-Speed, Low-Side Gate Driver
Operational Waveforms
At power up, the driver output remains low until the VDD voltage reaches the turn-on threshold. The magnitude of the OUT pulses rises with VDD until steady-state VDD is reached. The non-inverting operation illustrated in Figure 40 shows that the output remains low until the UVLO threshold is reached, then the output is in-phase with the input.
The total power dissipation in a gate driver is the sum of three components; PGATE, PQUIESCENT, and PDYNAMIC: (1) PTOTAL = PGATE + PDYNAMIC Gate Driving Loss: The most significant power loss results from supplying gate current (charge per unit time) to switch the load MOSFET on and off at the switching frequency. The power dissipation that results from driving a MOSFET at a specified gatesource voltage, VGS, with gate charge, QG, at switching frequency, fSW , is determined by: PGATE = QG * VGS * FSW (2) Dynamic Pre-drive / Shoot-through Current: A power loss resulting from internal current consumption under dynamic operating conditions, including pin pull-up / pull-down resistors, can be obtained using the graphs in Figure 11 and Figure 12 in Typical Performance Characteristics to determine the current IDYNAMIC drawn from VDD under actual operating conditions: PDYNAMIC = IDYNAMIC * VDD (3) Once the power dissipated in the driver is determined, the driver junction temperature rise with respect to the device lead can be evaluated using thermal equation:
Figure 40. Non-Inverting Start-Up Waveforms For the inverting configuration of Figure 39, start-up waveforms are shown in Figure 41. With IN+ tied to VDD and the input signal applied to IN-, the OUT pulses are inverted with respect to the input. At power up, the inverted output remains low until the VDD voltage reaches the turn-on threshold, then it follows the input with inverted phase.
TJ = PTOTAL * JL + TC (4) where: TJ = driver junction temperature JL = thermal resistance from junction to lead TL = lead temperature of device in application. In a typical forward converter application with 48V input, as shown in Figure 42, the FDS2672 would be a potential MOSFET selection. The typical gate charge would be 32nC with VGS = VDD = 10V. Using a TTL input driver at a switching frequency of 500kHz, the total power dissipation can be calculated as: PGATE = 32nC * 10V * 500kHz = 0.160W PDYNAMIC = 6.5mA * 10V = 0.065W PTOTAL = 0.225W (5) (6) (7)
The 5-pin SOT23 has a junction-to-lead thermal resistance JL = 95C/W. In a system application, the localized temperature around the lead of the device is a function of the layout and construction of the PCB along with airflow across the surfaces. To ensure reliable operation, the maximum junction temperature of the device must be prevented from exceeding the maximum rating of 150C; with 80% derating, TJ would be limited to 120C. Rearranging Equation 4 determines of the maximum lead temperature at the PCB surface to maintain the junction temperature below 120C: TL = TJ - PTOTAL * JL (8) TL = 120C - 0.225W * 95 C/W = 99C (9) For comparison purposes, replace the 5-pin SOT23 used in the previous example with the 6-pin MLP package with JL = 4.5C/W referenced to Pin 5. The 6pin MLP package can operate with a lead temperature on the PCB surface of 118C, while maintaining the junction temperature below 120C. This illustrates that the physically smaller MLP package with thermal pad offers a more conductive path to remove the heat from the driver. Consider the tradeoffs between reducing overall circuit size with junction temperature reduction for increased reliability.
www.fairchildsemi.com 14
Figure 41. Inverting Start-Up Waveforms
Thermal Guidelines
Gate drivers used to switch MOSFETs and IGBTs at high frequencies can dissipate significant amounts of power. It is important to determine the driver power dissipation and the resulting junction temperature in the application to ensure that the part is operating within acceptable temperature limits.
(c) 2007 Fairchild Semiconductor Corporation FAN3100 * Rev. 1.0.0
FAN3100 -- Single 2A High-Speed, Low-Side Gate Driver
Typical Application Diagrams
Figure 42. Forward Converter, Primary-Side Gate Drive (MLP Package Shown)
Figure 43. Driver for Two-Transistor Forward Converter Gate Transformer
Figure 44. Secondary Synchronous Rectifier Driver
VDD R IN C FAN3100C OUT
Delay IN OUT
Figure 45. Programmable Time Delay Using CMOS Input
(c) 2007 Fairchild Semiconductor Corporation FAN3100 * Rev. 1.0.0 www.fairchildsemi.com 15
FAN3100 -- Single 2A High-Speed, Low-Side MOSFET Driver
Table 1. Related Products Part Number
FAN3100C FAN3100T FAN3226C FAN3226T FAN3227C FAN3227T FAN3228C FAN3228T FAN3229C FAN3229T FAN3223C FAN3223T FAN3224C FAN3224T FAN3225C FAN3225T
Type
Gate Drive Input (Sink/Src) Threshold
CMOS TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL
Logic
One Channel of Dual-Input/Single-Output One Channel of Dual-Input/Single-Output Dual Inverting Channels + Dual Enable Dual Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Two Channels of Dual-Input/Single-Output, Pin Config.1 Two Channels of Dual-Input/Single-Output, Pin Config.1 Two Channels of Dual-Input/Single-Output, Pin Config.2 Two Channels of Dual-Input/Single-Output, Pin Config.2 Dual Inverting Channels + Dual Enable Dual Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Two Channels of Dual-Input/Single-Output Two Channels of Dual-Input/Single-Output
Package
SOT23-5, MLP6 SOT23-5, MLP6 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8
Single 2A +2A / -1.5A Single 2A +2A / -1.5A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 4A Dual 4A Dual 4A Dual 4A Dual 4A Dual 4A +2A / -1.5A +2A / -1.5A +2A / -1.5A +2A / -1.5A +2A / -1.5A +2A / -1.5A +2A / -1.5A +2A / -1.5A +4A / -3A +4A / -3A +4A / -3A +4A / -3A +4A / -3A +4A / -3A
(c) 2007 Fairchild Semiconductor Corporation FAN3100 * Rev. 1.0.0
www.fairchildsemi.com 16
FAN3100 -- Single 2A High-Speed, Low-Side MOSFET Driver
Physical Dimensions
Figure 46. 2x2mm, 6-Lead Molded Leadless Package (MLP)
(c) 2007 Fairchild Semiconductor Corporation FAN3100 * Rev. 1.0.0
www.fairchildsemi.com 17
FAN3100 -- Single 2A High-Speed, Low-Side MOSFET Driver
Physical Dimensions (Continued)
SYMM C L 0.95 0.95
3.00 2.80
5 4
A
B
3.00 2.60 1.70 1.50 2.60
1
2
3
(0.30) 0.95 1.90 0.50 0.30 0.20 CAB 0.70 1.00
TOP VIEW
LAND PATTERN RECOMMENDATION
SEE DETAIL A
1.30 0.90 0.15 0.05
1.45 MAX
C 0.10 C
0.22 0.08
NOTES: UNLESS OTHEWISE SPECIFIED
GAGE PLANE 0.25 8 0 0.55 0.35 0.60 REF
A) THIS PACKAGE CONFORMS TO JEDEC MO-178, ISSUE B, VARIATION AA, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) MA05Brev5
SEATING PLANE
Figure 47. 5-Lead SOT-23
(c) 2007 Fairchild Semiconductor Corporation FAN3100 * Rev. 1.0.0 www.fairchildsemi.com 18
FAN3100 -- Single 2A High-Speed, Low-Side MOSFET Driver
(c) 2007 Fairchild Semiconductor Corporation FAN3100 * Rev. 1.0.0
www.fairchildsemi.com 19

▲Up To Search▲

Price & Availability of FAN3100

	To Download FAN3100 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .